DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 246

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

7.4.12
Ending DMA Transfer
The operation for ending DMA transfer depends on the transfer end conditions. When DMA
transfer ends, the DA bit in DMMDR changes from 1 to 0, indicating that DMA transfer has
ended.
Transfer End by 1 → 0 Transition of DMTCR: When the value of DMTCR changes from 1 to
0, DMA transfer ends on the corresponding channel and the DA bit in DMMDR is cleared to 0. If
the TCEIE bit in DMMDR is set at this time, a transfer end interrupt request is generated by the
transfer counter and the IRF bit in DMMDR is set to 1.
In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in DMTCR changes
from 1 to 0.
DMA transfer does not end if the DMTCR value has been 0 since before the start of transfer.
Transfer End by Repeat Area Overflow Interrupt: If an address overflows the repeat area
when a repeat area specification has been made and repeat interrupts have been enabled (with the
SARIE or DARIE bit in DMACR), a repeat area overflow interrupt is requested. DMA transfer
ends, the DA bit in DMMDR is cleared to 0, and the IRF bit in DMMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
Transfer End by 0-Write to DA Bit in DMMDR: When 0 is written to the DA bit in DMMDR
by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress
or a transfer request was accepted.
In block transfer mode, DMA transfer halts after completion of one-block-size transfer.
The DA bit in DMMDR is not cleared to 0 until all transfer processing has ended. Up to that point,
the value of the DA bit will be read as 1.
Transfer Abort by NMI Interrupt: DMA transfer is aborted when an NMI interrupt is
generated. The DA bit is cleared to 0 in all channels. In external request mode, DMA transfer is
performed for all transfer requests for which DRAK has been output. In dual address mode,
processing is executed for the write cycle following the read cycle.
In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the
transfer is halted midway through a block, the BEF bit in DMMDR is set to 1 to indicate that the
block transfer was not carried out normally.
Rev. 2.00, 03/04, page 212 of 534