DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 197

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit
6
5
4
Bit Name
IRF
TCEIE
SDIR
0
0
0
Initial
Value
R/W
R/(W)*
R/W
R/W
2
Transfer Counter End Interrupt Enable
Single Address Direction
Description
Interrupt Request Flag
Flag indicating that an interrupt request has occurred
and transfer has ended.
To clear this bit, the DA bit in DMMDR is set to 1 or 0 is
written after reading 1 from this bit.
0: No interrupt request
[Clearing conditions]
•
•
1: Interrupt request occurrence
[Setting conditions]
•
•
•
Enables or disables transfer end interrupt requests by
the transfer counter. When transfer ends according to
the transfer counter while this bit is set to 1, the IRF bit
in DMMDR is set to 1, indicating that an interrupt
request has occurred.
0: Transfer end interrupt requests by transfer counter
1: Transfer end interrupt requests by transfer counter
Specifies the data transfer direction in single address
mode. In dual address mode (AMS = 0), the
specification by this bit is ignored.
0: Transfer direction: DMSAR → external device with
1: Transfer direction: External device with DACK →
are disabled
are enabled
DACK
DMDAR
Writing 1 to the DA bit in DMMDR
Writing 0 to IRF after reading IRF = 1
Transfer end interrupt request generated by transfer
counter
Source address repeat area overflow interrupt
request
Destination address repeat area overflow interrupt
request
Rev. 2.00, 03/04, page 163 of 534