DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 192

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.3.1
DMSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the DMSAR value is ignored
when a device with DACK is specified as the transfer source.
The upper 8 bits of DMSAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
The DMSAR value is undefined at a reset or in hardware standby mode.
Do not write to DMSAR for a channel on which DMA transfer is in progress.
DMSAR can be read at all times by the CPU. When reading DMSAR for a channel on which
DMA transfer processing is in progress, a longword-size read must be executed.
7.3.2
DMDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
DMDAR value is ignored when a device with DACK is specified as the transfer destination.
The upper 8 bits of DMDAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
The DMDAR value is undefined at a reset or in hardware standby mode.
Do not write to DMDAR for a channel on which DMA transfer is in progress.
DMDAR can be read at all times by the CPU. When reading DMDAR for a channel on which
DMA transfer processing is in progress, a longword-size read must be executed.
7.3.3
DMTCR specifies the number of transfers. The function differs according to the transfer mode
(normal/block).
The DMTCR value is undefined at a reset or in hardware standby mode.
Do not write to DMTCR for a channel on which DMA transfer is in progress.
Rev. 2.00, 03/04, page 158 of 534
DMA Source Address Register (DMSAR)
DMA Destination Address Register (DMDAR)
DMA Transfer Count Register (DMTCR)

Related parts for DF2170BVTE33V