DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 441

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Programming Procedure in User Program Mode: The procedures for download, initialization,
and programming are shown in figure 14.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 14.4.4, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
procedure program
Set SCO to 1 and
execute download
Start programming
specify download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
DPFR = 0?
Initialization
FPFR = 0?
parameter
1
Yes
Yes
Initialization error processing
Download error processing
No
No
Figure 14.11 Programming Procedure
1.
2.
3.
4.
5.
6.
7.
8.
No
JSR FTDAR setting + 16
Disable interrupts and bus
Set parameters to ER1
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
Rev. 2.00, 03/04, page 407 of 534
Clear FKEY to 0
master operation
programming is
other than CPU
Programming
Required data
FPFR = 1?
completed?
and ER0
1
Yes
Yes
Clear FKEY and
error processing
No
programming
9.
10.
11.
12.
13.
14.
15.