DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 385

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.5.5
EP2 has two 64-byte FIFOs in full-speed mode and two 512-byte FIFOs in high-speed mode, but
the user can transmit data and write transmit data without being aware of this dual-FIFO
configuration. However, one data write should be performed for one FIFO. For example, even if
both FIFOs are empty, it is not possible to write the number of transmit data in PKTE2 at one time
after consecutively writing 128 bytes of data in full-speed mode or 1024 bytes of data in high-
speed mode. The number of transmit data must be written in PKTE2 for each 64-byte write in full-
speed mode or 512-byte write in high-speed mode. Make sure to confirm that the EP2EMPTY bit
in IFR0 is set to 1 before writing data.
When performing bulk-in transfer is required, write 1 to the EP2 EMPTY bit in IER0 first and
then enable the EP2 FIFO empty interrupt. At first, both EP2 FIFOs are empty, and so an EP2
FIFO empty interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, the EP2 EMPTY bit is cleared to 0. If at
least one FIFO is empty, the EP2 EMPTY bit in IFR0 is set to 1. When ACK is returned from the
host after data transmission is completed, the FIFO used in the data transmission becomes empty.
If the other FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to the EP2 EMPTY bit in IER0 and
disable interrupt requests.
Note: The dual-configured FIFOs are handled in packet units. Therefore, even if either of FIFOs
is empty because of a short packet, when the number of transmit data is written in the
packet enable register 2 (PKTE2), both FIFOs become full.
EP2 Bulk-In Transfer (Dual FIFO)
Rev. 2.00, 03/04, page 351 of 534