DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 234

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

DREQ Pin Low Level Activation Timing: Figure 7.31 shows an example of single address mode
transfer activated by the DREQ pin low level.
DREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
DMMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the DREQ pin while acceptance via the DREQ pin is possible, the
request is held within the DMAC. Then when activation is initiated within the DMAC, the request
is cleared. At the end of the single cycle, acceptance resumes and DREQ pin low level sampling is
performed again; this sequence of operations is repeated until the end of the transfer.
Rev. 2.00, 03/04, page 200 of 534
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in DMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of single cycle.
Figure 7.31 Example of Single Address Mode Transfer Activated by DREQ Pin Low Level
Acceptance after transfer enabling;
(As in [1],
φ
Address bus
DMA control
Channel
Idle
pin low level is sampled at rise of φ, and request is held.)
[1]
Minimum 3 cycles
Request
Bus release
[2]
clearance period
Single
[3]
Request
DMA single
Transfer source/
destination
Idle
pin low level is sampled at rise of φ, and request is held.
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
clearance period
Single
[6]
Request
DMA single Bus release
Transfer source/
destination
Idle
Acceptance
resumed
[7]