DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 24

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Figure 6.3 Read Strobe Negation Timing (Example of 3-State Access Space) ............................ 93
Figure 6.4 RAS Signal Assertion Timing
Figure 6.5 Area Divisions........................................................................................................... 102
Figure 6.6 Address Format ......................................................................................................... 103
Figure 6.7 Address Map ............................................................................................................. 105
Figure 6.8 CSn Signal Output Timing (n = 3 to 0) ..................................................................... 108
Figure 6.9 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 109
Figure 6.10 Access Sizes and Data Alignment Control (16-bit Access Space) .......................... 110
Figure 6.11 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 111
Figure 6.12 Bus Timing for 8-Bit, 3-State Access Space ........................................................... 112
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)........... 113
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)............ 114
Figure 6.15 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ................................ 115
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 116
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)............ 117
Figure 6.18 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 118
Figure 6.19 Example of Wait State Insertion Timing................................................................. 119
Figure 6.20 Example of Read Strobe Timing ............................................................................. 120
Figure 6.21 Example of Timing when Chip Select Assertion Period is Extended ..................... 121
Figure 6.22 DRAM Basic Access Timing (RAST = 0, CAST = 0)............................................ 124
Figure 6.23 Example of Access Timing with 3-State Column Address Output Cycle
Figure 6.24 Example of Access Timing when RAS Signal Goes Low from Beginning of
Figure 6.25 Example of Timing with One Row Address Output Hold State
Figure 6.26 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)....... 128
Figure 6.27 Example of Wait State Insertion Timing (2-State Column Address Output) .......... 129
Figure 6.28 Example of Wait State Insertion Timing (3-State Column Address Output) .......... 130
Figure 6.29 2-CAS Control Timing (Write Access to Even Address: RAST = 0, CAST = 0) ... 131
Figure 6.30 Example of 2-CAS DRAM Connection .................................................................. 132
Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) ............................... 133
Figure 6.32 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) ............................... 133
Figure 6.33 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)......... 135
Figure 6.34 Example of Idle Cycle Insertion when RAS Down Mode cannot be Continued..... 135
Figure 6.35 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0).............. 136
Figure 6.36 RTCNT Operation................................................................................................... 137
Figure 6.37 Compare Match Timing .......................................................................................... 138
Figure 6.38 CBR Refresh Timing............................................................................................... 138
Figure 6.39 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)................. 138
Figure 6.40 Self-Refresh Timing ................................................................................................ 139
Rev. 2.00, 03/04, page xxii of xxxii
(2-State Column Address Output Cycle, Full Access)................................................. 97
(RAST = 0).............................................................................................................. 125
T
(RAST = 0, CAST = 0)........................................................................................... 127
r
State (CAST = 0) ................................................................................................ 126