DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 32

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Section 6 Bus Controller (BSC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Section 7 DMA Controller (DMAC)
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Section 8 I/O Ports
Table 8.1
Section 9 8-Bit Timer (TMR)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Section 10 Watchdog Timer (WDT)
Table 10.1
Section 11 Serial Communication Interface for Boot Mode (SCI)
Table 11.1
Table 11.2
Table 11.3
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Section 12 Universal Serial Bus 2 (USB2)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Rev. 2.00, 03/04, page xxx of xxxii
Pin Configuration .................................................................................................. 85
Address Map ....................................................................................................... 104
Bus Specifications for Each Area (Basic Bus Interface) ..................................... 106
Data Buses Used and Valid Strobes .................................................................... 110
DRAM Interface Pins.......................................................................................... 123
Idle Cycles in Mixed Accesses to Normal Space and DRAM Space.................. 148
Pin States in Idle Cycle ....................................................................................... 149
Pin Configuration ................................................................................................ 156
DMAC Transfer Modes ...................................................................................... 171
DMAC Channel Priority ..................................................................................... 186
Interrupt Sources and Priority Order ................................................................... 213
Port Functions ..................................................................................................... 220
Pin Configuration ................................................................................................ 265
Clock Input to TCNT and Count Condition ........................................................ 268
8-Bit Timer Interrupt Sources ............................................................................. 275
Timer Output Priorities ....................................................................................... 279
Switching of Internal Clock and TCNT Operation ............................................. 280
WDT Interrupt Source......................................................................................... 288
Pin Configuration ................................................................................................ 292
Relationships between N Setting in BRR and Bit Rate B ................................... 300
BRR Settings for Various Bit Rates (Asynchronous Mode) (1).......................... 301
BRR Settings for Various Bit Rates (Asynchronous Mode) (2).......................... 302
Maximum Bit Rate for Each Frequency (Asynchronous Mode)......................... 303
Serial Transfer Formats (Asynchronous Mode) .................................................. 305
SSR Status Flags and Receive Data Handling..................................................... 311
SCI Interrupt Sources .......................................................................................... 314
Input/Output Signals ........................................................................................... 321
Request Decoding by Firmware .......................................................................... 354
Tree Configuration .............................................................................................. 358
FIFO Size in Each Transfer Mode ...................................................................... 366
Relation between Settings of Bits MXC2 to MXC0 and
Address Multiplexing ......................................................................................... 122