DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 176

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.7
6.7.1
When this LSI accesses external address space, it can insert an idle cycle (T
in the following three cases: (1) when read accesses in different areas occur consecutively or when
an external access cycle occurs after a single address transfer, (2) when (1) occurs and a write
cycle occurs immediately after a read cycle, and (3) when (1) and (2) occur and a read cycle
occurs immediately after a write cycle. A condition for idle cycle insertion can be selected with
the IDLE1 and IDLE0 bits in BCR. The number of idle cycles to be inserted can be set from one
to four states by setting the IDLC1 and IDLC0 bits in BCR. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, etc., with a long output floating
time, and high-speed memory, I/O interfaces, and so on.
Rev. 2.00, 03/04, page 142 of 534
Read
Write
Figure 6.43 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1)
Idle Cycle
Operation
φ
Address bus
Data bus
Data bus
(
(
(
(
(
,
)
)
)
)
)
T
p
Row address
High
High
T
r
T
c1
Column address
T
c2
i
) between bus cycles
T
c3