DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 363

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.3.3
IER0 enables the interrupt request indicated in the interrupt flag register. When an interrupt flag is
set while the corresponding bit in IER0 is set to 1, an interrupt request selected by the interrupt
select register is asserted.
12.3.4
EPSZ0o is a receive data size register for endpoint 0o. EPSZ0o indicates the number of bytes of
data to be received from the host.
Bit
31 to 25
24
23 to 17
16
15 to 10
9
8
7
6
5
4
3
2
1
0
Bit
31 to 0
EP0o Receive Data Size Register (EPSZ0o)
Interrupt Enable Register 0 (IER0)
Bit Name



EP3TR
EP3TS
BRST
EP2TR
EP2EMPTY 0
EP1FULL
SETUPTS
EP0oTS
EP0iTR
EP0iTS
Bit Name
D31 to D0
MODE F
VBUS F
Initial
Value
All 0
0
All 0
0
All 0
0
0
0
0
0
0
0
0
0
Initial
Value
—
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Reserved
The write value should always be 0.
Enables the MODE F interrupt.
Reserved
The write value should always be 0.
Enables the VBUS F interrupt.
Reserved
The write value should always be 0.
Enables the EP3TR interrupt.
Enables the EP3TS interrupt.
Enables the BRST interrupt.
Enables the EP2TR interrupt.
Enables the EP2EMPTY interrupt.
Enables the EP1FULL interrupt
Enables the SETUPTS interrupt.
Enables the EP0oTS interrupt.
Enables the EP0iTR interrupt.
Enables the EP0iTS interrupt.
Description
EP0o Receive Data Size
Rev. 2.00, 03/04, page 329 of 534