DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 509
DF2170BVTE33V
Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170BVTE33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Clearing with the RES pin
• Clearing with the STBY pin
Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS2 to
STS0 in SBYCR should be set as described below.
• Using a crystal resonator
• Using an external clock
Table 16.2 Operating Frequency and Standby Time
Note:
Software Standby Mode Application Example: Figure 16.2 shows an example in which a
transition is made to software standby mode at the falling edge on the NMI pin, and software
standby mode is cleared at the rising edge on the NMI pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
STS2
0
1
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Set bits STS2 to STS0 so that the standby time is more than the oscillation stabilization time.
Table 16.2 shows the standby times for operating frequencies and settings of bits STS2 to
STS0.
A PLL circuit stabilization time is necessary. Refer to table 16.2 to set the standby time.
: Recommended setting time
*
STS1
0
1
0
1
This setting must not be used in the flash memory version.
STS0
0
1
0
1
0
1
0
1
Standby Time
8192 states
16384 states
32768 states
65536 states
131072 states
262144 states
Reserved
16 states*
10 MHz
0.8
1.6
3.2
6.5
13.1
26.2
1.6
20 MHz
0.4
0.8
1.6
3.2
6.5
13.1
0.8
Rev. 2.00, 03/04, page 475 of 534
33 MHz
0.2
0.4
0.9
1.9
3.9
7.9
0.4
Unit
ms
µs
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