DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 156

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.6
In this LSI, external space area 2 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 10 Mbytes can be set by means of bit DSET in DRAMCR. Burst operation is also
possible, using fast page mode.
6.6.1
Area 2 is designated as DRAM space by setting bit DSET in DRAMCR to 1.
In DRAM space, the RAS signal is valid. The bus specifications for DRAM space such as the bus
width, number of wait states, and so on are determined according to the settings for area 2.
6.6.2
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.5 shows the relation between the settings of bits MXC2 to MXC0 and the shift size.
Table 6.5
Rev. 2.00, 03/04, page 122 of 534
Row
address
Column
address
MXC2 MXC1 MXC0 Shift Size
0
1
DRAM Interface
Setting DRAM Space
Address Multiplexing
DRAMCR
0
1
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
0
1
0
1
8 bits
9 bits
10 bits
11 bits
Reserved
(setting
prohibited)
A19 to
A16
A19 to
A16
A19 to
A16
A19 to
A16
A19 to
A16
A19 to
A16
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Pins
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