DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 129

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit
6
5
4, 3
Bit Name
RCDM
DDS

Initial
Value
0
0
All 0
R/W
R/W
R/W
R/W
RAS Down Mode
When access to DRAM space is interrupted by an
access to normal space, an access to an internal I/O
register, etc., this bit selects whether the RAS signal is
held low while waiting for the next DRAM access (RAS
down mode), or is driven high again (RAS up mode).
The setting of this bit is valid only when the BE bit is set
to 1.
If this bit is cleared to 0 when set to 1 in the RAS down
state, the RAS down state is cleared at that point, and
RAS goes high.
When using DRAM interface in RAS down mode and
RAS down state is not continued, a 1-state idle cycle is
inserted to drive RAS signal high.
0: RAS up mode selected for DRAM space access
1: RAS down mode selected for DRAM space access
Reserved
Description
DMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when DMAC single address
transfer is performed on the DRAM interface.
When the BE bit is cleared to 0 in DRAMCR, disabling
DRAM burst access, DMAC single address transfer is
performed in full access mode regardless of the setting
of this bit.
This bit has no effect on other bus master external
accesses or DMAC dual address transfers. If this bit is
set to 1, the DACK output timing is changed.
0: Full access is always executed
1: Burst access is enabled
These bits can be read from or written to. However, the
write value should always be 0.
Rev. 2.00, 03/04, page 95 of 534