DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 396

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

1. USSUSP Output Mask
2. Entering Suspend State by USB Module
3. USB Suspend Interrupt (USBI2)
Rev. 2.00, 03/04, page 362 of 534
Figure 12.17 Enter/Recover Sequence of USB Suspend State and Software Standby Mode
SUSRI interrupt request
USBI2 interrupt request
Internal suspend signal
When the USUSOUT bit in USBSUSP is cleared to 0, output of the USSUSP pin is masked
(fixed to 1) and notification of the suspend state to the external transceiver is disabled.
If the USB continues to be idle for the specified time, the USB module asserts the internal
suspend signal and enters the suspend state. Since the USSUSP output is masked by means of
the USUSOUT bit in USBSUSP, the external pin, USSUSP, is not changed.
When the USUSFGE bit in USBSUSP is set to 1 and the internal suspend signal of the USB
module is changed, an interrupt (USBI2) can be requested to the CPU.
As the initial setting, the USUSFG bit (interrupt flag) in USBSUSP should be cleared to 0 and
then the USUSFGE bit in USBSUSP should be set to 1.
The USBI2 interrupt request occurs when the internal suspend signal of the USB module is
changed. After the interrupt flag is cleared in the interrupt routine, monitor the USUSMONI bit
in USBSUSP and confirm that the interrupt occurs because of transition to the suspend state.
Note that an interrupt occurs when transition is made in the following order: normal mode,
suspend mode, and normal mode.
Initial setting
mask signal
USCLK
:
During the period other than the
[1]
φ
signal mask period.
[2]
[3]
Interrupt
flag
cleared
[4]
[5]
signal mask period, the internal suspend signal is inverted and output.
Software standby mode
Oscillation stabilization time
[6]
[7]
Interrupt
flag
cleared
Interrupt
flag
cleared
[8]