DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 179

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system's load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.47. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
Address bus
Address bus
Data bus
(area A)
(area B)
(area A)
(area B)
Overlap period between
and
φ
φ
Figure 6.47 Relationship between Chip Select (CS) and Read (RD)
Figure 6.46 Example of Idle Cycle Operation (Read after Write)
(a) No idle cycle insertion
(a) No idle cycle insertion
T
may occur
T
1
1
Bus cycle A
Bus cycle A
(IDLE1 = 0, IDLE0 = 0)
Long output floating time
(IDLE1 = 0, IDLE0 = 0)
T
T
y
2
2
T
T
3
3
Bus cycle B
Bus cycle B
T
T
(area B)
1
1
T
T
2
2
Data collision
Address bus
Address bus
Data bus
(area A)
(area B)
(area A)
(area B)
φ
φ
(b) Idle cycle insertion
(b) Idle cycle insertion
T
T
1
(IDLE1 = 0, IDLE0 = 0, IDLC1 = 0,
1
Bus cycle A
Bus cycle A
(IDLE1 = 0, IDLE0 = 0, IDLC1 = 0,
IDLC0 = 0)
Rev. 2.00, 03/04, page 145 of 534
IDLC0 = 0)
T
T
2
2
T
T
3
3
Idle cycle
Idle cycle
T
T
i
i
Bus cycle B
Bus cycle B
T
T
1
1
T
T
2
2