DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 379

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

2. Data Stage (Control-In)
The firmware first analyzes the request data that is sent from the host in the setup stage, and
determines the subsequent data stage direction. If the result of request data analysis is that the
data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If there
is more data to be sent, this data is written to the FIFO after the data written first has been sent
to the host (EP0i TS bit in IFR0 is set to 1).
The end of the data stage is identified when the host transmits an OUT token and the status
stage is entered.
Note: If the size of the data transmitted by the function is smaller than the data size requested by the host,
the function indicates the end of the data stage by returning to the host a packet shorter than the
maximum packet size. If the size of the data transmitted by the function is an integral multiple of the
maximum packet size, the function indicates the end of the data stage by transmitting a zero-length
packet.
(EP0i TS in IFR0 = 1)
Transmit data to host
Set EP0i transmit
Receive IN token
to SETUP TS in
in EP0i FIFO?
complete flag
USB function
Valid data
0 written
IFR0?
Figure 12.6 Data Stage Operation (Control-In)
Yes
Yes
ACK
No
No
NAK
NAK
Interrupt generated
data bytes to packet enable
data bytes to packet enable
Write number of transmit
Write number of transmit
Write data to EP0i data
Write data to EP0i data
(EP0i TS in IFR0 = 0)
register 0i (PKTE0i)
register 0i (PKTE0i)
Clear interrupt flag
Rev. 2.00, 03/04, page 345 of 534
register (EPDR0i)
register (EPDR0i)
From setup stage
every packet.
Firmware