DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 365

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.3.8
EPDR0s is a data register only for the setup request for endpoint 0. EPDR0s stores 8-byte request
data sent from the host in setup stage. Note that only request data to be processed by the
microcomputer is received. When a request processed by the USB automatically is received, data
is not stored.
When data reception is started in the next setup stage during reading, data is overwritten
unconditionally.
12.3.9
EPDR1 consists of two 512-byte receive FIFO buffers for endpoint 1. The size of EPDR1 is as
twice as the maximum packet size in high-speed mode and has a dual-FIFO configuration. When
there is no data in the single FIFO buffer, the USB returns the ACK handshake (both high-speed
and full-speed modes) to the host. When reception is completed and data is full in the both FIFO
buffers, the USB returns the NYET handshake (high-speed mode) or ACK handshake (full-speed
mode) to the host. The number of receive bytes is indicated in EPSZ1. DMA transfer can be
performed for receive data in EPDR1. EPDR1 can be initialized by setting the EP1CLR bit in the
FIFO clear register 0.
Though the 0-length packet can be received, the FIFO is not full, the ACK handshake (both high-
speed and full-speed modes) is returned to the host, and data is ignored. Therefore the EP1 FULL
status flag in IFR0 is not set.
12.3.10 EP2 Data Register (EPDR2)
EPDR2 consists of two 512-byte transmit FIFO buffer for endpoint 2. The size of EPDR2 is as
twice as the maximum packet size in high-speed mode and has a dual-FIFO configuration. When
transmit data is written in EPDR2 and number of transmit data is written in the packet enable
register 2 (PKTE2), one packet of transmit data is valid and the buffer is switched. DMA transfer
can be performed for transmit data to EPDR2. EPDR2 can be initialized by setting the EP2CLR
bit in the FIFO clear register 0.
Bit
31 to 0
Bit
31 to 0
EP1 Data Register (EPDR1)
EP0s Data Register (EPDR0s)
Bit Name
D31 to D0 All 0
Bit Name
D31 to D0 All 0
Initial
Value
Initial
Value
R/W
R
R/W
R
Description
Data Register only for EP0 Setup Request
Description
Two 512-byte Receive FIFO Buffers for EP1
Rev. 2.00, 03/04, page 331 of 534