DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 369

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit
5
4
3, 2
1
0
Bit Name
EP2CLR
EP1CLR

EP0oCLR
EP0iCLR
Initial
Value
0
0
All 0
0
0
R/W
W
R
W
W
W
W
R
Description
EP2 Clear
1 is written when clearing EP2 IN FIFO. Writing 0 is
invalid and no operation is performed.
EP2 FIFO Clear Status
[Setting condition]
This bit is set to 1 when the EP2 FIFO is forcibly cleared
by the FCLR register. When this bit is set to 1, access to
the EP2 FIFO is prohibited. This bit is cleared to 0
automatically after the FIFO is internally cleared. Confirm
that this bit is cleared to 0 and then wait for at least four
cycles, before accessing to the EP2.
[Clearing condition]
This bit cannot be cleared because this bit is a status bit.
EP1 Clear
1 is written when clearing EP1 OUT FIFO. Writing 0 is
invalid and no operation is performed.
Reserved
The write value should always be 0.
EP0o Clear
1 is written when clearing EP0o OUT FIFO. Writing 0 is
invalid and no operation is performed.
EP0i Clear
1 is written when clearing EP0i IN FIFO. Writing 0 is
invalid and no operation is performed.
EP0i FIFO Clear Status
[Setting condition]
This bit is set to 1 when the EP0i FIFO is forcibly cleared
by the FCLR register. When this bit is set to 1, access to
the EP0i FIFO is prohibited. This bit is cleared to 0
automatically after the FIFO is internally cleared. Confirm
that this bit is cleared to 0 and then wait for at least four
cycles, before accessing to the EP0i.
[Clearing condition]
This bit cannot be cleared because this bit is a status bit.
Rev. 2.00, 03/04, page 335 of 534