DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 207

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Single Address Mode: In single address mode, the DACK signal is used instead of the source or
destination address register to transfer data directly between an external device and external
memory. In this mode, the DMAC accesses the transfer source or transfer destination external
device by outputting the external I/O strobe signal (DACK), and at the same time accesses the
other external device in the transfer by outputting an address. In this way, DMA transfer can be
executed in one bus cycle. In the example of transfer between external memory and an external
device with DACK shown in figure 7.3, data is output to the data bus by the external device and
written to external memory in the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the SDIR bit in DMMDR. Transfer is performed from
the external memory (DMSAR) to the external device with DACK when SDIR = 0, and from the
external device with DACK to the external memory (DMDAR) when SDIR = 1.
The setting in the source or destination address register not used in the transfer is ignored.
The DACK pin becomes valid automatically when single address mode is selected.
The DACK pin is active-low. TEND pin output can be enabled or disabled by means of the
TENDE bit in DMMDR. TEND is output for one bus cycle.
Figure 7.3 shows the data flow in single address mode, and figure 7.4 shows an example of the
timing.
φ
Address bus
Figure 7.2 Example of Timing in Dual Address Mode
read cycle
DMSAR
DMA
write cycle
DMDAR
DMA
Rev. 2.00, 03/04, page 173 of 534