DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 178

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Read after Write: If an external read occurs after an external write while the IDLE1 and IDLE0
bits in BCR are set to B'11, an idle cycle which is set by the IDLC1 and IDLC0 bits in BCR is
inserted at the start of the read cycle.
Figure 6.46 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a collision occurs in bus cycle B between the CPU write data and read data from the SRAM.
In (b), an idle cycle is inserted, and a data collision is prevented.
Rev. 2.00, 03/04, page 144 of 534
Address bus
Data bus
(area A)
(area B)
φ
Figure 6.45 Example of Idle Cycle Operation (Write after Read)
T
1
(a) No idle cycle insertion
Bus cycle A
Long output floating time
(IDLE1 = 0, IDLE0 = 0)
T
2
y
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
Data bus
(area A)
(area B)
φ
(b) Idle cycle insertion
T
1
Bus cycle A
(IDLE1 = 0, IDLE0 = 0, IDLC1 = 0,
IDLC0 = 0)
T
2
T
3
Idle cycle
T
i
Bus cycle B
T
1
T
2