DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 93

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.4
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI and IRQ7 to IRQ0) and internal interrupt sources
from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see
section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
4.5
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
Table 4.3
Interrupt Control Mode
0
1
stack.
from the vector table to the PC, and program execution begins from that address.
stack.
from the vector table to the PC, and program execution starts from that address.
Interrupt Exception Handling
Trap Instruction Exception Handling
Status of CCR after Trap Instruction Exception Handling
I
Set to 1
Set to 1
CCR
UI
Retains value prior to execution
Set to 1
Rev. 2.00, 03/04, page 59 of 534

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