DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 14

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.7
6.8
6.9
6.10 Bus Controller Operation in Reset .................................................................................... 152
Section 7 DMA Controller (DMAC)................................................................. 153
7.1
7.2
7.3
7.4
7.5
7.6
Rev. 2.00, 03/04, page xii of xxxii
6.6.8
6.6.9
6.6.10 Byte Access Control ............................................................................................ 131
6.6.11 Burst Operation.................................................................................................... 132
6.6.12 Refresh Control.................................................................................................... 137
6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 140
Idle Cycle.......................................................................................................................... 142
6.7.1
6.7.2
Write Data Buffer Function .............................................................................................. 150
Bus Arbitration ................................................................................................................. 151
6.9.1
6.9.2
Features............................................................................................................................. 153
Input/Output Pins.............................................................................................................. 155
Register Descriptions........................................................................................................ 157
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
Operation .......................................................................................................................... 171
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10 DMAC Bus Cycles (Single Address Mode) ........................................................ 196
7.4.11 Examples of Operation Timing in Each Mode .................................................... 201
7.4.12 Ending DMA Transfer ......................................................................................... 212
7.4.13 Relationship between DMAC and Other Bus Masters ........................................ 213
Interrupt Sources............................................................................................................... 213
Usage Notes ...................................................................................................................... 216
DMA Transfer Requests
(Auto Request Mode/External Request Mode/USB Transfer Request) ............... 176
Precharge State Control ....................................................................................... 128
Wait Control ........................................................................................................ 129
Operation ............................................................................................................. 142
Pin States in Idle Cycle........................................................................................ 149
Operation ............................................................................................................. 151
Bus Transfer Timing............................................................................................ 151
DMA Source Address Register (DMSAR).......................................................... 158
DMA Destination Address Register (DMDAR) .................................................. 158
DMA Transfer Count Register (DMTCR)........................................................... 158
DMA Mode Control Register (DMMDR) ........................................................... 160
DMA Address Control Register (DMACR) ........................................................ 165
USB Transfer Control Register (USTCR) ........................................................... 169
Transfer Modes.................................................................................................... 171
Address Modes (Dual Address Mode/Single Address Mode) ............................. 172
Bus Modes (Cycle Steal Mode/Burst Mode) ....................................................... 177
Transfer Modes (Normal Transfer Mode/Block Transfer Mode) ........................ 178
Repeat Area Function .......................................................................................... 179
Registers during DMA Transfer Operation ......................................................... 182
Channel Priority................................................................................................... 186
DMAC Bus Cycles (Dual Address Mode)........................................................... 189