DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 364

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.3.5
EPSZ1 is a receive data size register for endpoint 1. EPSZ1 indicates the number of bytes of data
to be received from the host. The FIFO for endpoint 1 has a dual-FIFO configuration. The data
size indicated by this register refers to the currently selected FIFO.
12.3.6
EPDR0i is a 64-byte transmit FIFO buffer for endpoint 0. EPDR0i stores number of packets of
transmit data for control-in. If one packet of data is written and number of transmit data is written
in the packet enable register 0i (PKTE0i), transmit data is valid. If data is transmitted and then the
ACK handshake is returned from the host, the EP0iTS bit in IFR0 is set. EPDR0i can be initialized
by setting the EP0iCLR bit in the FIFO clear register 0. When the setup is received, EPDR0i is
cleared. After the setup data is received, transmission is impossible until the SETUP TS bit is
cleared.
12.3.7
EPDR0o is a 64-byte receive FIFO buffer for endpoint 0 and has a single FIFO buffer. When
reception is completed, the USB returns the NYET handshake (high-speed mode) or ACK
handshake (full-speed mode) to the host. EPDR0o stores receive data for endpoint 0 except for the
setup request. When data is received normally, the EP0oTS bit in IFR0 is set and the number of
receive bytes is indicated in the EP0o receive data size register. After the setup data is received,
reception is impossible until the SETUP TS bit is cleared.
Though the 0-length packet can be received, the ACK handshake (both high-speed and full-speed
modes) is returned to the host and data is ignored. However, the EP0oTS flag in IFR0 is set.
Rev. 2.00, 03/04, page 330 of 534
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
EP1 Receive Data Size Register (EPSZ1)
EP0i Data Register (EPDR0i)
EP0o Data Register (EPDR0o)
Bit Name
D31 to D0 —
Bit Name
D31 to D0 All 0
Bit Name
D31 to D0 All 0
Initial
Value
Initial
Value
Initial
Value
R/W
R
R/W
W
R/W
R
Description
Description
Description
EP1 Receive Data Size
64-Byte Transmit FIFO Buffer for EP0
64-Byte Receive FIFO Buffer for EP0