DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 157

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.6.3
If the ABW2 bit in ACSCR is set to 1, that area is designated as 8-bit DRAM space; if the bit is
cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit
configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
6.6.4
Table 6.6 shows the pins used for DRAM interfacing and their functions. Although the CS2 pin is
in the input state after a reset, the RAS signal is output after the DSET bit in DRAMCR is set and
DRAM space is designated.
For details, refer to section 8, I/O Ports.
Table 6.6
Pin
HWR
CS2
UCAS
LCAS
RD
A15 to A0
D15 to D0
Data Bus
Pins Used for DRAM Interface
DRAM Interface Pins
With DRAM
Setting
WE
RAS
UCAS
LCAS
OE
A15 to A0
D15 to D0
Name
Write enable
Row address strobe
Upper column address
strobe
Lower column address
strobe
Output enable
Address pins
Data pins
I/O
Output
Output
Output
Output
Output
Output
I/O
Rev. 2.00, 03/04, page 123 of 534
Function
Write enable for DRAM space
access
Row address strobe when area
2 is designated as DRAM space
Upper column address strobe
for 16-bit DRAM space access
or column address strobe for 8-
bit DRAM space access
Lower column address strobe
signal for 16-bit DRAM space
access
Output enable signal for DRAM
space access
Row address/column address
multiplexed output
Data input/output pins