DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 194

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

7.3.4
DMMDR specifies the operating mode and transfer type.
Rev. 2.00, 03/04, page 160 of 534
Bit
15
Bit Name
DA
DMA Mode Control Register (DMMDR)
Initial
Value
0
R/W
R/(W)*
1
Description
DMA Active
Controls the DMA operation. When this bit is set to 1,
this indicates that an DMA operation is in progress.
When auto request mode is specified (by bits MDS1
and MDS0), transfer processing begins when this bit is
set to 1. With external requests, transfer processing
begins when a transfer request is issued after this bit
has been set to 1. When this bit is cleared to 0 during
an DMA operation, transfer is halted. If this bit is
cleared to 0 during an DMA operation in block transfer
mode, transfer processing is continued for the currently
executing one-block transfer, and the bit is cleared on
completion of the currently executing one-block
transfer.
If an external source that ends (aborts) transfer occurs,
this bit is automatically cleared to 0 and transfer is
terminated. Do not change the operating mode, transfer
method, or other parameters while this bit is set to 1.
0: Data transfer disabled on corresponding channel
[Clearing conditions]
•
•
•
•
1: Data transfer enabled on corresponding channel and
during an DMA operation.
When the specified number of transfers end
When operation is halted by a repeat area overflow
interrupt
When 0 is written to DA while DA = 1
(In block transfer mode, write is effective after end
of one-block transfer)
Reset, NMI interrupt, hardware standby mode