DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 218

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

DA Bit in DMMDR: The DA bit in DMMDR is written to by the CPU to control enabling and
disabling of data transfer, but may be cleared automatically by the DMAC due to the DMA
transfer status. There are also periods during transfer when a 0-write to the DA bit by the CPU is
not immediately effective.
Conditions for DA bit clearing by the DMAC include the following:
• When the DMTCR value changes from 1 to 0, and transfer ends
• When a repeat area overflow interrupt is requested, and transfer ends
• When an NMI interrupt is generated, and transfer halts
• A reset
• Hardware standby mode
• When 0 is written to the DA bit, and transfer halts
When transfer is halted by writing 0 to the DA bit, the DA bit remains at 1 during the DMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the DA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0
is written to the DA bit. The DA bit remains set to 1 from the time of the 0-write until the end of
the last DMA cycle. Writes (except to the DA bit) are prohibited to registers of a channel for
Rev. 2.00, 03/04, page 184 of 534
DMTCR in normal transfer mode
DMTCR
DMTCR
DMTCR in block transfer mode
DMTCR
DMTCR
Figure 7.11 DMTCR Update Operations in Normal Transfer Mode and
23
23
23
23
Block
Block
size
size
16
16
1 to H'FFFFFF
Before update
Before update
15
15
0
1 to H'FFFF
Block Transfer Mode
0
0
0
0
0
Fixed
Fixed
–1
–1
23
23
23
23
Block
Block
size
size
16
16
0 to H'FFFFFE
After update
After update
15
15
0
0 to H'FFFE
0
0
0
0
0