DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 221

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode: If transfer
requests for different channels are issued during a transfer in auto request cycle steal mode, the
operation depends on the channel priority. If the channel that made the transfer request is of higher
priority than the channel currently performing transfer, the channel that made the transfer request
is selected. If the channel that made the transfer request is of lower priority than the channel
currently performing transfer, that channel's transfer request is held pending, and the currently
transferring channel remains selected.
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus master other than the DMAC at this time, a cycle for the other
bus master is initiated. If there is no other bus request, the bus is released for one cycle.
Figure 7.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
Address bus
DMA control
Channel 0
Channel 1
Channel 2
φ
Idle
Request
Request
Request cleared
held
held
Figure 7.13 Example of Channel Priority Timing
Channel 0
Selected
selected
Not
Request
Channel 0 transfer
Request cleared
held
Channel 0
Channel 1
Selected
release
Bus
Channel 1 transfer
Request cleared
Channel 1
Rev. 2.00, 03/04, page 187 of 534
Channel 2
release
Bus
Channel 2 transfer
Channel 2

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