DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 97

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

5.1
• Two interrupt control modes
• Priorities settable with ICR
• Independent vector addresses
• Nine external interrupts
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI.
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for IRQ7 to IRQ0.
Internal interrupt sources
WOVI0 to USBI2
Features
[Legend]
ICR :
ISCR :
IER :
ISR :
SYSCR :
NMI input
IRQ input
SYSCR
Interrupt control register
IRQ sense control register
IRQ enable register
IRQ status register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
Section 5 Interrupt Controller
Interrupt controller
NMIEG
INTM1, INTM0
ISCR
NMI input
IRQ input
ISR
IER
determination
ICR
Priority level
Rev. 2.00, 03/04, page 63 of 534
Vector number
Interrupt
request
I, UI
CPU
CCR