PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 105

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

new data is available in the transmit FIFO. Inserted SYN characters are not part of the
frame and thus not used for CRC calculation.
4.5.4
4.5.4.1
If enabled via register
transmitted with a selectable number of repetitions after interframe-time-fill transmission
is stopped and a new frame is ready to be sent out.
Note: If the preamble pattern equals the SYN pattern, reception is triggered by the
4.6
When operating in the auto mode, the SCC offers a high degree of protocol support. In
addition to address recognition, the SCC autonomously processes all (numbered) S- and
I-frames (window size 1 only) with either normal or extended control field format
(modulo-8 or modulo-128 sequence numbers – selectable via register
’MCS’).
The following functions will be performed:
– updating of transmit and receive counter
– evaluation of transmit and receive counter
– processing of S commands
– flow control with RR/RNR
– generation of responses
– recognition of protocol errors
– transmission of S commands, if acknowledgement is not received
– continuous status query of remote station after RNR has been received
– programmable timer/repeater functions.
In addition, all unnumbered frames are forwarded directly to the processor. The logical
link can be initialized by software at any time (Reset HDLC Receiver by RRES command
in register CMDRH).
Additional logical connections can be operated in parallel by software.
4.6.1
Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured
to function as a combined (primary/secondary) station, where they autonomously
perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol.
Data Sheet
preamble.
Special Functions
Preamble Transmission
Procedural Support (Layer-2 Functions)
Full-Duplex LAPB/LAPD Operation
CCR2H
, a programmable 8-bit pattern (register
105
Detailed Protocol Description
PREAMB
PEB 20532
PEF 20532
CCR2H
2000-09-14
) is
bit