PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 132

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
Data Sheet
Register 10
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 11
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
7
7
0
0
GPISL
GPP Interrupt Status Register (Low Byte)
GPISH
GPP Interrupt Status Register (High Byte)
GP6I
6
6
0
read only
00
0A
written by SEROCCO-M, read and evaluated by CPU
read only
00
0B
written by SEROCCO-M, read and evaluated by CPU
H
H
H
H
5
5
0
0
GPP Interrupt Status Bits
GPP Interrupt Status Bits
5-132
4
4
0
0
3
3
0
0
Register Description (GPISL)
GP10I
GP2I
2
2
GP9I
GP1I
1
1
PEB 20532
PEF 20532
2000-09-14
GP8I
GP0I
0
0

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