PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 175

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
Data Sheet
Register 29
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
PRE(7:0)
Bit
H
A
B
7
0
Preamble
This bit field determines the preamble pattern which is send out during
preamble transmission.
Note: In HDLC-mode, zero-bit insertion is disabled during preamble
PREAMB
Preamble Register
6
transmission.
0
read/write
00
Channel A
1E
written by CPU;
read and evaluated by SEROCCO-M
H
H
5
0
Channel B
6E
H
Preamble Pattern
5-175
4
0
PRE(7:0)
PRE(7:0)
3
0
Register Description (PREAMB)
2
0
(hdlc/bisync modes)
1
0
PEB 20532
PEF 20532
2000-09-14
0
0

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