PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 229

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Register 85
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The Receive Status Byte ’RSTA’ contains comprehensive status information about the
last received frame (HDLC/PPP) or the last received ASYNC/BISYNC character.
The SCC attaches this status byte to the receive data and thus it should be read from
the RFIFO.
In HDLC/PPP modes the RSTA value can optionally be read from this register address;
in ASYNC and BISYNC modes a read to this register is not specified. In extended
transparent mode this status field does not apply.
Data Sheet
Bit
H
A
B
VFR
PE
PE
7
Receive Status Byte
RSTA
RDO
FE
6
0
read only
00
Channel A
58
written by SEROCCO-M to RFIFO;
read from RFIFO and evaluated by CPU
H
H
CRCOK
5
0
0
Channel B
A8
Receive Status Byte
H
RAB
4
0
0
229
3
0
0
HA(1:0)/
SU(1:0)
2
0
0
Register Description
C/R
1
0
0
PEB 20532
PEF 20532
2000-09-14
LA
P
P
0