PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 191

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

PEB 20532
PEF 20532
Register Description (PCMTX3)
PCMTX
PCM Mask for Transmit Direction
(all mode)
This bit field is valid in clock mode 5 only and the PCM mask must be
enabled via bit ’TEPCM’ in register TTSA1.
Each bit selects one of 32 (8-bit) transmit time-slots. The offset of time-
slot zero to the frame sync pulse can be programmed via register
TTSA1
bit field ’TTSN’.
Data Sheet
5-191
2000-09-14