PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 263

no-image

PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
Figure 64
Figure 65
Figure 66
Data Sheet
(1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with
(1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with
(1) Signal BHE only available in 16-bit Infineon/Intel bus mode
DACK asserted.
DACK asserted.
DACK
DACK
A(7:0)
BHE
CS
CS
DRR
DRT
WR
ALE
RD
WR
RD
1)
1)
1)
Infineon/Intel DMA Read Cycle Timing
Infineon/Intel DMA Write Cycle Timing
Infineon/Intel Multiplexed Address Timing
20
22
21
23
232
last write access to
last read access to
19
18
Electrical Characteristics
XFIFO
RFIFO
PEB 20532
PEF 20532
2000-09-14

Related parts for PEF 20532 F V1.3