PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 38

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Table 3
Pin No.
Table 4
Pin No.
Data Sheet
P-TQFP-
100-3
91
8
7
P-TQFP-
100-3
23
24
25
26
Serial Port Pins (cont’d)
General Purpose Pins
Symbol In (I)
RxDB
XTAL1
XTAL2
Symbol In (I)
GP10
GP9
GP8
GP6
Out (O)
I
I
O
Out (O)
I/O
Function
Receive Data Channel B
(corresponding to channel A)
Crystal Connection
If the internal oscillator is used for clock
generation (clock modes 0b, 6, 7) the external
crystal has to be connected to these pins. The
internal oscillator should be powered up
(GMODE:OSCPD = ’0’) and the signal shaper
may be activated (GMODE:DSHP = ’0’).
Moreover, XTAL1 may be used as input for a
common clock source to both SCCs, provided by
an external clock generator (oscillator). In this
case the oscillator unit may be powered down and
it is recommended to bypass the shaper of the
internal oscillator unit by setting bit ’DSHP’ to ’1’.
A pull-down resistor to V
pin XTAL1 if not used.
Function
General Purpose Pins
These pins serve as general purpose input/output
pins.
38
SS
is recommended for
Pin Descriptions
PEB 20532
PEF 20532
2000-09-14