PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 68

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

PEB 20532
PEF 20532
Functional Overview
Interference Rejection and Spike Filtering
Two or more edges in the same directional data stream within a time period of 16
reference clocks are considered to be interference and consequently no additional clock
adjustment is performed.
Phase Adjustment (PA)
Referring to
Figure
28,
Figure 29
and
Figure
30, in the case where an edge appears in
the data stream within the PA fields of the time window, the phase will be adjusted by 1/
16 of the data.
Phase Shift (PS) (NRZ, NRZI only)
Referring to
Figure 28
in the case where an edge appears in the data stream within the
PS field of the time window, a second sampling of the bit is forced and the phase is
shifted by 180 degrees.
Note: Edges in all other parts of the time window will be ignored.
This operation facilitates a fast and reliable synchronization for most common
applications. Above all, it implies a very fast synchronization because of the phase shift
feature: one edge on the received data stream is enough for the DPLL to synchronize,
thereby eliminating the need for synchronization patterns, sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of the
clock recovery cannot be guaranteed.
The SCC offers the option to disable the Phase Shift function for NRZ and NRZI
encodings by setting bit ’PSD’ in register
CCR0L
to ’1’. In this case, the PA fields are
extended as shown in
Figure
29.
Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach
the optimal sampling position. To ensure correct data sampling, preambles should
precede the data information.
Figure
28,
Figure 29
and
Figure 30
explain the DPLL algorithms used for the different
data encodings.
Data Sheet
68
2000-09-14