PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 252

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 59
Data Sheet
Packet n, Buffer 0:
Packet n, Buffer 1:
Packet n, Buffer m:
(write transmit byte count with command
(write transmit byte count with command
Fragmented DMA Transmission (Multiple Buffers per Packet)
(prepare external DMA controller
(prepare external DMA controller
(prepare external DMA controller
CPU / MEMORY
(write transmit byte count with
<XBC> transmit data
<XBC> transmit data
<XBC> transmit data
with buffer base address)
with buffer base address)
with buffer base address)
ALLS interrupt (optional)
DMA transfer of
DMA transfer of
DMA transfer of
command bit 'XF')
TDTE interrupt
TDTE interrupt
TDTE interrupt
bit 'XF'+'XME')
bytes
bytes
bytes
bit 'XF')
...
...
...
252
XBC
TFIFO
TFIFO
TFIFO
XBC
TFIFO
TFIFO
TFIFO
XBC
TFIFO
TFIFO
TFIFO
SEROCCO-M
Programming
PEB 20532
PEF 20532
2000-09-14