PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 96

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 46
4.4.2
The SCC offers the flexibility to combine clock modes, data encoding and data sampling
in many different ways. However, only definite combinations make sense and are
recommended for correct operation:
4.4.2.1
Prerequisites:
• Bit clock rate 16 selected (register
• Clock mode 0, 1, 3b, 4, or 7b selected (register
• NRZ data encoding selected (register
The receiver which operates with a clock rate equal to 16 times the nominal (expected)
data bit rate, synchronizes itself to each character by detecting and verifying the start bit.
Since character length, parity and stop bit length is known, the ensuing valid bits are
sampled. Oversampling (3 samples) around the nominal bit center in conjunction with
majority decision is provided for every received bit (including start bit).
The synchronization lasts for one character, the next incoming character causes a new
synchronization to be performed. As a result, the demand for high clock accuracy is
reduced. Two communication stations using the asynchronous procedure are clocked
independently, their clocks need not be in phase or locked to exactly the same frequency
but, in fact, may differ from one another within a certain range.
4.4.2.2
Prerequisites:
• Bit clock rate 1 selected (register
Data Sheet
1
Start
Bit
Data Reception
Asynchronous Mode
Isochronous Mode
Asynchronous Character Frame
(LSB)
D0
5 to 8 Data Bits
(6 to 9 Bits with Parity)
D1
D2
D3
CCR0L
Character Frame
CCR0L
CCR0H
D4
96
bit BCR = ‘0’)
, bit BCR = ‘1’)
D5
Par.
, bit field ’SC’)
CCR0L
D6
Par.
Detailed Protocol Description
, bit field ’CM’)
D7
Par.
Parity
1 or 2
Stop
Bits
PEB 20532
PEF 20532
2000-09-14
ITD01804