PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 41

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

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The functional blocks of SEROCCO-M can be divided into two major domains:
– the microprocessor interface of SEROCCO-M provides access to on-chip registers
– the Serial Communication Controller (SCC) is capable of processing bit-synchronous
Data exchange between the serial communication controller and the microprocessor
interface is performed using FIFOs, decoupling these two domains.
3.1
Figure 8
Data Sheet
and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally
these FIFOs can be accessed by an external 4-channel DMA controller.
(HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully
transparent data traffic.
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Functional Overview
Block Diagram
External DMA
Block Diagram
Interface
Transmit FIFO
Transmit FIFO
Receive FIFO
Receive FIFO
(32 Byte)
(32 Byte)
(32 Byte)
(32 Byte)
JTAG Test
Interface
5
Serial Channel A
Serial Channel B
Transmit FIFO
Receive FIFO
(32 Byte)
(32 Byte)
41
LAP Control
Transmit
Machine
Machine
Protocol
Receive
Protocol
TSA
Functional Overview
Decoder/
Collision
Detection
DPLL
Clock
Control
Oscillator
BRG
PEB 20532
PEF 20532
2000-09-14
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