PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 203

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 63
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 64
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
7
7
0
0
0
0
RAL1
Receive Address 1 Low Register
RAH1
Receive Address 1 High Register
6
6
0
0
0
0
read/write
00
Channel A
40
written by CPU; read and evaluated by SEROCCO-M
read/write
00
Channel A
41
written by CPU; read and evaluated by SEROCCO-M
H
H
H
H
5
5
0
0
0
0
RAH1
Channel B
90
Channel B
91
Receive Address 1 (high)
Receive Address 1 (low)
H
H
5-203
4
4
0
0
0
0
or RAH1
RAL1
RAL1
3
3
0
0
0
0
Register Description (RAL1)
2
2
0
0
0
0
CRI
1
1
0
0
0
0
PEB 20532
PEF 20532
2000-09-14
RAH1_0
0
0
0
0
0
0