PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 272

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
7.7.2.4
Figure 74
Table 26
No. Parameter
110 Receive strobe to RxCLK setup
111 Receive strobe to RxCLK hold
112 Transmit strobe to RxCLK setup
113 Transmit strobe to RxCLK hold
114 TxD to RxCLK delay
115 TxD to RxCLK high impedance delay
Data Sheet
(1) No bus configuration mode and bus configuration mode 1
(2) Bus configuration mode 2
(3) TxD Idle is either active high or high impedance if ’open drain’ output type is selected.
(RxStrobe)
(TxStrobe)
(Note1,3)
(Note2,3)
(Note1)
RxCLK
TxCLK
RxD
TxD
Clock Mode 1 Strobe Timing
TxD
CD
Clock Mode 1
Clock Mode 1
110
112
valid
Strobe Timing
Strobe Timing
111
113
241
114
114
min.
5
5
5
5
10
10
Electrical Characteristics
Limit Values
115
max.
25
25
PEB 20532
PEF 20532
2000-09-14
115
Unit
ns
ns
ns
ns
ns
ns

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