PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 28

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
2.2
Table 1
Pin No.
Data Sheet
P-TQFP-
100-3
81
80
79
78
75
74
73
72
67
66
65
64
61
60
59
58
29
30
31
32
36
37
38
Pin Definitions and Functions
Microprocessor Bus Interface
Symbol In (I)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
A4
A3
A2
A1
Out (O)
I/O
I
I
I
I
I
I
I
Function
Data Bus
The data bus lines are bi-directional tri-state lines
which interface with the system’s data bus.
Address Bus
These pins connect to the system’s address bus
to select one of the internal registers for read or
write.
28
Pin Descriptions
PEB 20532
PEF 20532
2000-09-14

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