PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 178

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 33
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 34
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
17
1F
7
7
0
0
0
0
ACCM2
PPP ASYNC Control Character Map2
ACCM3
PPP ASYNC Control Character Map 3
1E
16
6
6
0
0
0
0
read/write
00
Channel A
22
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
23
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
ASYNC Character Control Map 17..10
ASYNC Character Control Map 1F..18
1D
15
5
5
0
0
0
0
Channel B
72
Channel B
73
H
H
1C
14
5-178
4
4
0
0
0
0
1B
13
3
3
0
0
0
0
Register Description (ACCM2)
1A
12
2
2
0
0
0
0
11
19
1
1
0
0
0
0
PEB 20532
PEF 20532
2000-09-14
10
18
0
0
0
0
0
0