PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 239

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
Data Sheet
RE
DRMBS
RMBS(11:0) Receive Maximum Buffer Size
Receive DMA Enable
Only valid if external DMA controller support is enabled.
Self-clearing command bit:
RE=’0’
RE=’1’
Disable Receive Maximum Buffer Size (RMBS) Check
Only valid if external DMA controller support is enabled.
DRMBS=’0’
DRMBS=’1’
Only valid if external DMA controller support is enabled.
The size of the receive buffer in host memory can be set up in this bit field
to ensure that request for DMA transfers are inhibited when the
maximum buffer size is reached. An RBF interrupt is generated (if
unmasked) to inform the CPU. If the external DMA controller supports
this function, it can be disabled by setting bit ’DRMBS’ to ’1’.
The DMA controller is not set up to forward receive data
into a buffer in memory.
Setting this bit to ’1’ enables the DMA support logic to
request the external DMA controller to transfer receive
data when available in RFIFO.
Evaluation of bit field RMBS(11:0) is enabled.
Evaluation of bit field RMBS(11:0) is disabled.
239
Register Description
PEB 20532
PEF 20532
2000-09-14

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