PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 146

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 19
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 20
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The command register contains self-clearing command bits. The command bits read a
’1’ until the corresponding command is executed completely.
Bit
Bit
H
A
B
H
A
B
RMC
RMC
RMC
STI
STI
STI
7
7
Timer
CMDRL
Command Register (Low Byte)
TRES
TRES
TRES
CMDRH
Command Register (High Byte)
RNR
6
6
0
0
read/write
00
Channel A
14
written by CPU, evaluated by SEROCCO-M
read/write
00
Channel A
15
written by CPU, evaluated by SEROCCO-M
H
H
H
H
TXON
XIF
5
5
0
0
0
0
Channel B
64
Channel B
65
Receiver Commands
H
H
XRES
XRES
XRES
5-146
4
4
0
0
0
Transmitter Commands
RSUC
HUNT
XF
XF
XF
3
3
0
Register Description (CMDRL)
XME
XME
XME
2
2
0
0
0
RFRD
RFRD
XREP
XREP
XREP
1
1
0
PEB 20532
PEF 20532
2000-09-14
TXOFF
RRES
RRES
RRES
0
0
0
0