PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 50

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Clock Modes
3.2.3.1
Separate, externally generated receive and transmit clocks are supplied to the SCC via
their respective pins. The transmit clock may be directly supplied by pin TxCLK
(clock mode 0a) or generated by the internal baud rate generator from the clock supplied
at pin XTAL1 (clock mode 0b).
In clock mode 0b the resulting transmit clock can be driven out to pin TxCLK if enabled
via bit ’TOE’ in register CCR0L.
Figure 14
Data Sheet
Clock Mode 0 (0a/0b)
clock mode 0a
clock mode 0b
Clock Mode 0a/0b Configuration
f
K=(n+1)/2
BRG
or
= f
OSC
OSC
M
/k
Ctrl.
Ctrl.
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
50
(tx clock monitor output)
Functional Overview
clock supply
clock supply
1
2
1
PEB 20532
PEF 20532
2000-09-14