PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 173

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
RFDF
Receive FIFO Data Format
In ASYNC mode, the character format is determined as follows:
RFDF='0'
Data Byte:
P
(no parity bit stored)
P: Parity bit stored in data byte (can be disabled via bit 'DPS')
PE: Parity Error
FE: Frame Error
P: Parity bit stored in status byte
7
7
7
7
P
6
6
P
5
5
Char8
4
Char7
Char6
Char5
0
0
0
0
5-173
RFDF='1'
Data Byte (DB):
P
(no parity bit stored)
7
7
7
7
P
6
6
P
5
5
Char8
4
Char7
Char6
Register Description (CCR3H)
Char5
0
0
0
0
(async/bisync mode)
PE
PE
PE
PE
Status Byte (SB):
7
7
7
7
FE
FE
FE
FE
6
6
6
6
PEB 20532
PEF 20532
2000-09-14
P
P
P
P
0
0
0
0