PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 48

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) should
The first two columns of
and bit ’SSEL’ in register CCR0L.
For example, clock mode 6b is choosen by writing a ’6’ to register CCR0L.CM(2:0) and
by setting bit CCR0L.SSEL equal to ’1’. The following 4 columns (grouped as ’Clock
Sources’) specify the source of the internal clocks. Columns REC and TRM correspond
to the domain clock frequencies f
The columns grouped as ’Control Sources’ cover additional clock mode dependent
control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or
synchronization signals (clock mode 5). The last column describes the function of signal
TxCLK which in some clock modes can be enabled as output signal monitoring the
effective transmit clock or providing a time slot control signal (clock mode 5).
The following is an example of how to read
For clock mode 6b (row ’6b’) the TRM clock (column ’TRM’) is supplied by the baudrate
generator (BRG) output divided by 16 (source BRG/16). The BRG (column ’BRG’) is
derived from the internal oscillator which is supplied by pin XTAL1 and XTAL2.
The REC clock (column ’REC’) is supplied by the internal DPLL which itself is supplied
by the baud rate generator (column ’DPLL’) again.
Note: The REC clock is DPLL clock divided by 16.
If enabled by bit ’TOE’ in register
via pin TxCLK (last column, row ’6b’).
Data Sheet
be enabled by clearing bit GMODE:OSCPD. This allows connection of an external
crystal to pins XTAL1-XTAL2. The output signal of the OSC can be used for one
serial channel, or for both serial channels (independent baud rate generators and
DPLLs). Moreover, XTAL1 alone can be used as input for an externally generated
clock.
Table 8
list all possible clock modes configured via bit field ’CM’
REC
CCR0L
and f
the resulting transmit clock can be monitored
TRM
48
Table
.
8:
Functional Overview
PEB 20532
PEF 20532
2000-09-14