PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 148

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
TXOFF
TXON
XRES
XF
Transmit Off Command
Self-clearing command bit:
This command bit is significant if in-band flow-control is selected.
TXOFF=’1’
Transmit On Command
Self-clearing command bit:
This command bit is significant if in-band flow-control is selected.
TXON=’1’
Transmitter Reset Command
Self-clearing command bit:
XRES=’1’
Transmit Frame
This self-clearing command bit is significant in interrupt driven operation
only (GMODE.EDMA=’0’).
XF=’1’
Forces the transmitter to enter its ’transmit off’ state. This
is equal to receiving an XOFF character.
Forces the transmitter to enter its ’transmit on’ state. This
is equal to receiving an XON character.
The SCC transmit FIFO is cleared and the transmitter
protocol engines are reset to their initial state.
A transmitter reset command is recommended after all
changes in protocol mode configurations (e.g. switching
between the protocol engines HDLC/ASYNC/BISYNC or
sub-modes of HDLC).
After having written up to 32 bytes to the XFIFO, this
command initiates transmission. In packet oriented
protocols like HDLC/PPP the opening flag is automatically
added by SEROCCO-M. If the end of the packet is part of
the transmit data, bit ’XME’ should be set in addition.
DMA Mode
After having written the length of the data block to be
transmitted to registers
initiates the data transfer from host memory to
SEROCCO-M by DMA. Transmission on the serial side
starts as soon as 32 bytes are transferred to the XFIFO or
the transmit byte counter value is reached.
5-148
XBCL
Register Description (CMDRH)
and XBCH, this command
(async mode)
(async mode)
PEB 20532
PEF 20532
(all modes)
(all modes)
2000-09-14