PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 159

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
CAS
TSCM
Carrier Detect Auto Start
CAS = ’0’
CAS = ’1’
Note: (1) In clock mode 1, 4 and 5 this bit must be set to ’0’.
Time Slot Control Mode
This bit controls internal counter operation in time slot oriented clock
mode 5:
TSCM=’0’
TSCM=’1’
(2) A receive clock must be provided for the autonomous receiver
control function of the CD input pin.
(3) In ASYNC mode the transmitter is additionally controlled by in-
band flow control mechanism (if enabled).
The CD pin is used as general input.
In clock mode 1, 4 and 5, clock mode specific control
signals must be provided at this pin (receive strobe,
receive gating RCG, frame sync clock FSC).
A pull-up/down resistor is recommended if unused.
The CD pin enables/disables the receiver for data
reception. (Polarity of CD pin can be configured via bit
’ICD’.)
The internal counter keeps running, restarting with zero
after being expired.
The internal counter stops at its maximum value and
restarts with the next frame sync pulse again.
5-159
Register Description (CCR1H)
PEB 20532
PEF 20532
(all modes)
(all modes)
2000-09-14